The present invention relates to a semiconductor memory device and more particularly to a device having a large capacity and low cost.
A dynamic random-access memory (DRAM) is a typical semiconductor memory device of a large capacity. In the past, a typical DRAM has been arranged, in such a way that as shown in FIG. 2, a plurality of word-lines W are disposed in parallel with one another, a plurality of data-lines D are disposed so as to cross the wordlines W, and a memory cell MC is disposed at each of desired positions at intersections of the word-lines W and the data-lines D. One memory cell MC is generally made up of one storage capacitor Cs as storage means, and one MOS (metal oxide semiconductor) transistor M as a switch. Information of one binary digit (one bit) is stored in the form of the quantity of electric charge accumulated in the storage capacitor Cs. Moreover, each of the memory cells is connected to the associated dataline by the MOS transistor M, and a signal is transferred between the storage capacitor in each of the memory cells and the data-line, through the MOS transistor M.
The reading operation is carried out in the following manner. The data-line is precharged at a certain potential in a stand-by state, and the data-line is turned to a floating state, then the MOS transistor M is turned ON by the word-line. The electric charge accumulated in the storage capacitor Cs is re-allocated between a stray capacitance Cd of the data-line D and the capacitor Cs so that the potential at the data-line D is changed. It is judged whether the level of the signal on the data-line is "1" or "0" by sense means (not shown) connected to the data-line D. Normally, means for restoring the information destructively read out from the memory cell is provided in the data-line to make the potential level of the data-line go to a high potential corresponding to "1" or a low potential corresponding to "0" in accordance with the judgement result by the sense means. By reducing the potential at the word-line W, the electric charge corresponding to that potential is accumulated in the storage capacitor Cs. The sense means may perform the function of that restore means substitutely in some cases. Moreover, the writing operation can be performed in the same manner as in the restore operation by making the data-line go to the high or low potential by the store means.
As for a method of attaining a higher density of the DRAM, it has been proposed to make memory cells constructed in a three-dimensional manner to reduce its area. For example, a stacked capacitor memory cell (STC cell) is described in an article of 1978 IEDM, Digest of Technical Papers, pp. 348-351. In this structure, an area required for a silicon substrate to provide a storage capacitor may be substantially equal to an area of a connection hole between a MOS transistor and a storage electrode so that an area of the memory cell becomes small.
However, there is a limitation in reduction of the are of the memory cell by such improvements in the structure of the a storage capacitor. A one-transistor/ one-capacitor type memory cell requires a connection hole between the cell and a data-line, a gate portion of a MOS transistor, a connection hole between the MOS transistor and the storage node and a space for electrically insulating this memory cell from other memory cells. Therefore, the area of the memory cell depends on such elements.
There is proposed another method in which the structure of the MOS transistor is also constructed in a three-dimensional manner to reduce more area of the memory cell. However, in this method, the manufacturing process becomes complicated. As a result, the investment amount of the manufacturing facilities is increased and the yield of memory cells is lowered. Therefore, even if the area is reduced, the ratio of the cost to the storage capacity is not decreased by this method.